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19-2710; Rev 1; 4/03
KIT ATION EVALU E AILABL AV
2.488Gbps/2.667Gbps Clock and Data Recovery with Limiting Amplifier
Features
o 2.488Gbps and 2.667Gbps Input Data Rates o Reference Clock Not Required for Data Acquisition o Exceeds ANSI, ITU, and Bellcore SONET/SDH Jitter Specifications o 2.7mUIRMS Clock Jitter Generation o 10mVP-P Input Sensitivity Without Threshold Adjust o 0.65UIP-P High-Frequency Jitter Tolerance o 170mV Wide Input Threshold Adjust Range o Clock Holdover Capability Using FrequencySelectable Reference Clock o Serial Loopback Input Available for System Diagnostic Testing o Loss-of-Lock (LOL) Indicator o Small 5mm 5mm 32-Pin QFN Package
General Description
The MAX3874 is a compact, dual-rate clock and data recovery with limiting amplifier for OC-48 and OC-48 with FEC SONET/SDH applications. Without using an external reference clock, the fully integrated phaselocked loop (PLL) recovers a synchronous clock signal from the serial NRZ data input. The input data is then retimed by this recovered clock, providing a clean data output. An additional serial input (SLBI) is available for system-loopback diagnostic testing. Alternatively, this input can be connected to a reference clock to maintain a valid clock output in the absence of data transitions. The device also includes a loss-of-lock (LOL) output. The MAX3874 contains a vertical threshold control to compensate for optical noise due to EDFAs in DWDM transmission systems. The recovered data and clock outputs are CML with on-chip 50 back termination on each line. Its jitter performance exceeds all SONET/ SDH specifications. The MAX3874A is the MAX3874 with a voltage-controlled oscillator (VCO) centered at 2.0212GHz. The MAX3874 operates from a single +3.3V supply and typically consumes 580mW. It is available in a 5mm 5mm 32-pin QFN with exposed pad package and operates over the -40C to +85C temperature range.
MAX3874
Ordering Information
PART MAX3874EGJ MAX3874AEGJ** TEMP RANGE -40C to +85C -40C to +85C PINPACKAGE 32 QFN-EP* 32 QFN-EP* PKG CODE G3255-1 G3255-1
Applications
SONET/SDH Receivers and Regenerators Add/Drop Multiplexers Digital Cross-Connects SONET/SDH Test Equipment DWDM Transmission Systems Access Networks
*EP = Exposed pad. **Contains a VCO centered at 2.0212GHz.
Pin Configuration appears at end of data sheet.
Typical Application Circuit
+3.3V CFIL 0.068F VCC FILTER OUT+ 2.488Gbps DATA SDISLBI+ GND +3.3V VCTRL VREF *FUTURE PRODUCT 2.488Gbps SYSTEM LOOPBACK DATA SIS LREF +3.3V LOL RATESET GND SLBI+3.3V CAZ 0.1F +3.3V FIL VCC_VCO CAZSDI+ SDO+ SDOCML +3.3V
CAZ+ FREFSET VCC
MAX3745* OUTIN
MAX3874
SCLKO+ SCLKO-
CML
________________________________________________________________ Maxim Integrated Products
1
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2.488Gbps/2.667Gbps Clock and Data Recovery with Limiting Amplifier MAX3874
ABSOLUTE MAXIMUM RATINGS
Supply Voltage, VCC..............................................-0.5V to +5.0V Input Voltage Levels (SDI+, SDI-, SLBI+, SLBI-) ..............................(VCC - 1.0V) to (VCC + 0.5V) Input Current Levels (SDI+, SDI-, SLBI+, SLBI-)..............20mA CML Output Current (SDO+, SDO-, SCLKO+, SCLKO-) ...22mA Voltage at LOL, LREF, SIS, FIL, RATESET, FREFSET, VCTRL, VREF, CAZ+, CAZ-......................-0.5V to (VCC + 0.5V) Continuous Power Dissipation (TA = +85C) 32-Pin QFN (derate 21.3mW/C above +85C) .........1384mW Operating Junction Temperature Range ...........-55C to +150C Storage Temperature Range .............................-55C to +150C Processing Temperature (die) .........................................+400C Lead Temperature (soldering, 10s) .................................+300C
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
DC ELECTRICAL CHARACTERISTICS
(VCC = +3.0V to +3.6V, TA = -40C to +85C. Typical values at VCC = +3.3V, TA = +25C, unless otherwise noted.) (Note 1)
PARAMETER Supply Current INPUT SPECIFICATION (SDI, SLBI) Single-Ended Input Voltage Range Input Common-Mode Voltage Input Termination to VCC Differential Input Voltage Range (SDI) Threshold Adjustment Range Threshold Control Voltage Threshold Control Linearity Threshold Setting Accuracy Threshold Setting Stabiliity Maximum Input Current Reference Voltage Output CML Differential Output Impedance CML Output Common-Mode Voltage ICTRL VREF Figure 2 15mV |VTH| 80mV 80mV < |VTH| 170mV -18 -6 -12 -10 2.14 2.2 VTH VCTRL RIN VIS Figure 1 Figure 1 VCC 0.8 VCC 0.4 42.5 50 VCC + 0.4 VCC 57.5 V V SYMBOL ICC (Note 2) CONDITIONS MIN TYP 175 MAX 215 UNITS mA
THRESHOLD-SETTING SPECIFICATION (SDI) Threshold adjust enabled Figure 2 Figure 2 (Note 3) 50 -170 0.3 5 +18 +6 +12 +10 2.24 600 +170 2.1 mVP-P mV V % mV mV A V
CML OUTPUT SPECIFICATION (SDO, SCLKO) RO (Note 4) 85 100 VCC 0.2 115 V
2
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2.488Gbps/2.667Gbps Clock and Data Recovery with Limiting Amplifier
DC ELECTRICAL CHARACTERISTICS (continued)
(VCC = +3.0V to +3.6V, TA = -40C to +85C. Typical values at VCC = +3.3V, TA = +25C, unless otherwise noted.) (Note 1)
PARAMETER LVTTL Input High Voltage LVTTL Input Low Voltage LVTTL Input Current LVTTL Output High Voltage LVTTL Output Low Voltage VOH VOL IOH = +20A IOL = -1mA SYMBOL VIH VIL -10 2.4 0.4 CONDITIONS MIN 2.0 0.8 +10 TYP MAX UNITS V V A V V LVTTL INPUT/OUTPUT SPECIFICATION (LOL, LREF, RATESET, FREFSET)
MAX3874
Note 1: Note 2: Note 3: Note 4:
At -40C, DC characteristics are guaranteed by design and characterization. CML outputs open. Voltage applied to VCTRL pin is from 0.3V to 2.1V when input threshold is adjusted from +170mV to -170mV. RL = 50 to VCC.
AC ELECTRICAL CHARACTERISTICS
(VCC = +3.0V to +3.6V, TA = -40C to +85C. Typical values at VCC = +3.3V, TA = +25C, unless otherwise noted.) (Note 5)
PARAMETER Serial Input Data Rate Differential Input Voltage (SDI) Differential Input Voltage (SLBI) Jitter Transfer Bandwidth Jitter Peaking Sinusoidal Jitter Tolerance (MAX3874) Sinusoidal Jitter Tolerance (MAX3874A) Sinusoidal Jitter Tolerance with Threshold Adjust Enabled (Note 8) Jitter Generation Differential Input Return Loss (SDI, SLBI) Output Edge Speed CML Output Differential Swing Clock-to-Q Delay tCLK-Q JGEN -20log | S11 | tr, tf JBW JP VID SYMBOL CONDITIONS MAX3874 (RATESET = GND) MAX3874 (RATESET = VCC) MAX3874A Threshold adjust disabled, Figure 1 (Note 6) BER 10
-10
MIN
TYP 2.488 2.667 2.0212
MAX
UNITS Gbps
10 50 1.5 0.7
1600 800 2.0 0.1
mVP-P mVP-P MHz dB UIP-P
MAX3874 MAX3874A f JBW f = 100kHz f = 1MHz f = 10MHz f = 1MHz (Note 7) f = 10MHz (Note 7) f = 100kHz f = 1MHz f = 10MHz (Note 9) 100kHz to 2.5GHz 2.5GHz to 4GHz 20% to 80% RL = 100 differential (Note 10) 600 -40 3.1 0.62 0.44
8.0 0.93 0.65 >0.5 >0.3 7.1 0.82 0.54 2.7 16 15 110 800 1000 +40 4.0 mUIRMS dB UIP-P UIP-P
CML OUTPUT SPECIFICATION (SDO, SCLKO) ps mVP-P ps
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2.488Gbps/2.667Gbps Clock and Data Recovery with Limiting Amplifier MAX3874
AC ELECTRICAL CHARACTERISTICS (continued)
(VCC = +3.0V to +3.6V, TA = -40C to +85C. Typical values at VCC = +3.3V, TA = +25C, unless otherwise noted.) (Note 5)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
PLL ACQUISITION/LOCK SPECIFICATION Tolerated Consecutive Identical Digits Acquisition Time LOL Assert Time Low-Frequency Cutoff for DCOffset Cancellation Loop CLOCK HOLDOVER SPECIFICATION Reference Clock Frequency Maximum VCO Frequency Drift (Note 12) Table 4 400 ppm BER 10
-10
2000 1.0 2.3 4 10.0
Bits ms s kHz
Figure 4 (Note 11) Figure 4 CAZ = 0.1F
Note 5: Minimum and maximum AC characteristics are guaranteed by design and characterization using the MAX3874. Specifications apply to the MAX3874A only when noted. Note 6: Jitter tolerance is guaranteed (BER 10-10) within this input voltage range. Input threshold adjust is disabled with VCTRL connected to VCC. Note 7: Measurements limited by equipment capability. Note 8: Measured using a 100mVP-P differential swing with a 20mVDC offset and an edge speed of 145ps (4th-order Bessel filter with f3dB = 1.8GHz). Note 9: Measured with 10mVP-P differential input, 223 - 1 PRBS pattern at OC-48 with bandwidth from 12kHz to 20MHz. Note 10: Relative to the falling edge of the SCLKO+ (Figure 3). Note 11: Measured at OC-48 data rate using a 0.068F loop filter capacitor initialized to +3.6V. Note 12: Measured at OC-48 data rate under LOL condition with the CDR clock output set by the external reference clock.
Timing Diagrams
VCC + 0.4V 800mV VCC 5mV
VTH (mV) +188 +170 +152 THRESHOLD-SETTING STABILITY (OVERTEMPERATURE AND POWER SUPPLY)
VCC - 0.4V VCC
(a) AC-COUPLED SINGLE-ENDED INPUT
5mV
0.3 1.1
1.3 VCTRL (V) 2.1 THRESHOLDSETTING ACCURACY (PART-TO-PART VARIATION OVER PROCESS)
800mV VCC - 0.4V
-152 -170 -188
VCC - 0.8V
(b) DC-COUPLED SINGLE-ENDED INPUT
Figure 1. Definition of Input Voltage Swing
Figure 2. Relationship Between Control Voltage and Threshold Voltage
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2.488Gbps/2.667Gbps Clock and Data Recovery with Limiting Amplifier
Timing Diagrams (continued)
tCLK INPUT DATA SCLKO+ tCLK-Q LOL ASSERT TIME SDO LOL OUTPUT ACQUISITION TIME DATA DATA
MAX3874
Figure 3. Definition of Clock-to-Q Delay
Figure 4. LOL Assert Time and PLL Acquisition Time Measurement
Typical Operating Characteristics
(VCC = +3.3V, TA = +25C, unless otherwise noted.)
RECOVERED CLOCK AND DATA (2.488Gbps, 223 - 1 PATTERN, VIN = 10mVP-P)
MAX3874toc01
RECOVERED CLOCK AND DATA (2.67Gbps, 223 - 1 PATTERN, VIN = 10mVP-P)
MAX3874toc02
200mV/ div
200mV/ div
100ps/div
100ps/div
RECOVERED CLOCK JITTER (2.488Gbps)
MAX3874toc03
JITTER GENERATION vs. POWER-SUPPLY WHITE NOISE
MAX3874toc04
JITTER TOLERANCE (2.488Gbps, 223 - 1 PATTERN, VIN = 10mVP-P)
WITH ADDITIONAL 0.15UI OF DETERMINISTIC JITTER INPUT JITTER (UIP-P) 10
MAX3874 toc05
4.0 3.5 JITTER GENERATION (psRMS) 3.0 2.5 2.0 1.5 1.0 0.5 0.0 OC-48 PRBS = 223 - 1
100
1 BELLCORE MASK 0.1
10ps/div TOTAL WIDEBAND RMS JITTER = 1.60ps PEAK-TO-PEAK JITTER = 12.20ps
0
5
10
15
20
25
30
10k
100k
1M
10M
WHITE-NOISE AMPLITUDE (mVRMS)
JITTER FREQUENCY (Hz)
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2.488Gbps/2.667Gbps Clock and Data Recovery with Limiting Amplifier MAX3874
Typical Operating Characteristics (continued)
(VCC = +3.3V, TA = +25C, unless otherwise noted.)
JITTER TOLERANCE vs. INPUT AMPLITUDE (2.488Gbps, 223 - 1 PATTERN)
MAX3874toc06
JITTER TOLERANCE vs. INPUT DETERMINISTIC JITTER
MAX3874toc07
JITTER TOLERANCE vs. THRESHOLD ADJUST
SINUSOIDAL JITTER TOLERANCE (UIP-P) JITTER FREQUENCY = 10MHz 0.6 0.5 0.4 0.3 0.2 0.1 0 10 20 30 40 50 60 70 80 INPUT THRESHOLD (% AMPLITUDE) 90 INPUT DATA FILTERED BY A 1870MHz 4TH-ORDER BESSEL FILTER VIN = 100mVP-P 2.488Gbps 223 - 1 PATTERN
MAX3874toc08
0.8 0.7 JITTER TOLERANCE (UIP-P) JITTER FREQUENCY = 1MHz 0.6 0.5 0.4 JITTER FREQUENCY = 10MHz 0.3 0.2 0.1 0 1 1000 INPUT AMPLITUDE (mVP-P) 10 100 WITH ADDITIONAL 0.15UI DETERMINISTIC JITTER
1.0 SINUSOIDAL JITTER TOLERANCE (UIP-P) 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 0 0.05 0.20 0.25 DETERMINISTIC JITTER (UIP-P) 0.10 0.15 fJITTER = 10MHz fJITTER = 1MHz 223 - 1 PATTERN 2.488Gbps VIN = 10mVP-P
0.7
10,000
0.30
JITTER TRANSFER
MAX3874toc09
BIT-ERROR RATIO vs. INPUT AMPLITUDE
10
-3
MAX3874toc10
SUPPLY CURRENT vs. TEMPERATURE
200 195 190 185 180 175 170 165 160 155 150 145 140 -50 -25 0 25 50 TEMPERATURE (C) 75
MAX3874toc11
0.5 0 JITTER TRANSFER (dB) -0.5 -1.0 -1.5 -2.0 -2.5 -3.0 1k 10k 100k FREQUENCY (Hz) 1M CFIL = 0.068F PRBS = 223 - 1 2.488Gbps
10-2
BELLCORE MASK
BIT-ERROR RATIO
10-5 10
-6
10-7 10 10
-8 -9
10-10 10-11 10M 0
OC-48 PRBS = 223 - 1 1 2 3 4 5
SUPPLY CURRENT (mA)
10-4
100
INPUT VOLTAGE (mVP-P)
DIFFERENTIAL S11 vs. FREQUENCY
MAX3874 toc12
PULLIN RANGE (RATESET = 0)
2.9 2.8 FREQUENCY (GHz) 2.7 2.6 2.5 2.4 2.3 2.2
MAX3874toc13
0 -5 -10 S11 (dB) -15 -20 -25 -30 -35 -40 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 FREQUENCY (GHz)
3.0
2.1 2.0 4.0 -50 -25 0 25 50 75 100 AMBIENT TEMPERATURE (C)
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2.488Gbps/2.667Gbps Clock and Data Recovery with Limiting Amplifier
Pin Description
PIN 1, 4, 27 2 3 5 6 7 8 9 10, 11, 16, 25, 32 12 13, 18 14, 15 17 19 20 21, 24 22 23 26 28 NAME VCC SDI+ SDISLBI+ SLBISIS LREF LOL GND FIL N.C. RATESET SCLKOSCLKO+ SDOSDO+ FREFSET CAZ+ +3.3V Supply Voltage Positive Serial Data Input, CML Negative Serial Data Input, CML Positive System Loopback Input or Reference Clock Input, CML Negative System Loopback Input or Reference Clock Input, CML Signal Selection Input, LVTTL. Set low for normal operation, set high for system loopback. Lock-to-Reference Clock Input, LVTTL. Set high for PLL lock to serial data, set low for PLL lock to reference clock. Loss-of-Lock Output, LVTTL. Active low. Supply Ground PLL Loop-Filter Capacitor Input. Connect a 0.068F capacitor between FIL and VCC_VCO. Not Connected VCO Frequency Select Input, LVTTL (Tables 2, 3, and 4) Negative Serial Clock Output, CML Positive Serial Clock Output, CML Negative Serial Data Output, CML Positive Serial Data Output, CML Reference Clock Frequency Select Input, LVTTL (Tables 2, 3, and 4) Positive Capacitor Input for DC-Offset Cancellation Loop. Connect a 0.1F capacitor between CAZ+ and CAZ-. Negative Capacitor Input for DC-Offset Cancellation Loop. Connect a 0.1F capacitor between CAZ+ and CAZ-. +2.2V Bandgap Reference Voltage Output. Optionally used for threshold adjustment. Analog Control Input for Threshold Adjustment. Connect to VCC to disable threshold adjust. Ground. The exposed pad must be soldered to the circuit board ground for proper thermal and electrical performance. FUNCTION
MAX3874
VCC_VCO +3.3V Supply Voltage for the VCO
VCC_OUT Supply Voltage for the CML Outputs
29 30 31 EP
CAZVREF VCTRL Exposed Pad
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2.488Gbps/2.667Gbps Clock and Data Recovery with Limiting Amplifier MAX3874
Detailed Description
The MAX3874 consists of a fully integrated PLL limiting amplifier with threshold adjust, DC-offset cancellation loop, data retiming block, and CML output buffers (Figure 5). The PLL consists of a phase/frequency detector, a loop filter, and a VCO. This device is designed to deliver the best combination of jitter performance and power dissipation by using a fully differential signal architecture and low-noise design techniques.
SLBI Input Amplifier
The SLBI input amplifier accepts either NRZ loopback data or a reference clock signal. This amplifier can accept a differential input amplitude from 50mVP-P to 800mVP-P.
Phase Detector
The phase detector incorporated in the MAX3874 produces a voltage proportional to the phase difference between the incoming data and the internal clock. Because of its feedback nature, the PLL drives the error voltage to zero, aligning the recovered clock to the center of the incoming data eye for retiming.
SDI Input Amplifier
The SDI inputs of the MAX3874 accept serial NRZ data with a differential input amplitude from 10mV P-P to 1600mVP-P. The input sensitivity is 10mVP-P, at which the jitter tolerance is met for a BER of 10-10 with threshold adjust disabled. The input sensitivity can be as low as 4mV P-P and still maintain a BER of 10 -10 . The MAX3874 inputs are designed to directly interface with a transimpedance amplifier such as the MAX3745. For applications in which vertical threshold adjustment is needed, the MAX3874 can be connected to the output of an AGC amplifier such as the MAX3861. When using the threshold adjust, the input voltage range is 50mVP-P to 600mVP-P (see the Design Procedure section).
Frequency Detector
The digital frequency detector (FD) acquires frequency lock without the use of an external reference clock. The frequency difference between the received data and the VCO clock is derived by sampling the in-phase and quadrature VCO outputs on both edges of the datainput signal. Depending on the polarity of the frequency difference, the FD drives the VCO until the frequency difference is reduced to zero. Once frequency acquisition is complete, the FD returns to a neutral state. False locking is eliminated by this digital frequency detector.
CAZ+
CAZ-
LOL
FIL
RATESET
VREF
VCTRL
THRESHOLD ADJUST DC-OFFSET CANCELLATION LOOP
MAX3874
BANDGAP REFERENCE
SDI+ AMP SDI-
0 D 1 Q CML
SDO+ SDOPHASE/ FREQUENCY DETECTOR SCLKO+ VCO CML SCLKO-
SLBI+ AMP SLBI-
LOOP FILTER
SIS LREF FREFSET LOGIC
Figure 5. Functional Diagram
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2.488Gbps/2.667Gbps Clock and Data Recovery with Limiting Amplifier
Loop Filter and VCO
The phase detector and frequency detector outputs are summed into the loop filter. An external capacitor (CFIL) connected from FIL to VCC_VCO is required to set the PLL damping ratio. Note that the PLL jitter bandwidth does not change as the external capacitor changes, but the jitter peaking, acquisition time, and loop stability are affected. See the Design Procedure section for guidelines on selecting this capacitor. The loop filter output controls the two on-chip VCOs. The VCOs provide low phase noise and are trimmed to the 2.488GHz and 2.667GHz frequencies. (The MAX3874A uses a single VCO trimmed to 2.0212GHz.) The RATESET pin is used to select the appropriate VCO. See Tables 2, 3, and 4 for the proper settings.
Modes of Operation
The MAX3874 has three operational modes controlled by the LREF and SIS inputs: normal, system loopback, and clock holdover. Normal operation mode requires a serial data stream at the SDI inputs, system loopback mode requires a serial data stream at the SLBI inputs, and clock holdover mode requires a reference clock signal at the SLBI inputs. See Table 1 for the required LREF and SIS settings. Once an operational mode is chosen, the remaining logic inputs (RATESET, FREFSET) program the input data rate or reference clock frequency. Normal and System Loopback Settings The RATESET pin is available for setting the SDI and SLBI inputs to receive the appropriate data rate. The FREFSET pin can be set to a zero or 1 while in normal or system-loopback mode (Tables 2 and 3). Clock Frequencies in Holdover Mode Set the incoming reference-clock frequency and outgoing serial-clock frequency by setting RATESET and FREFSET appropriately (Table 3).
MAX3874
Loss-of-Lock Monitor
The LOL output indicates a PLL lock failure due to excessive jitter present at the data input or due to loss of input data. The LOL output is asserted low when the PLL loses lock.
DC-Offset Cancellation Loop
A DC-offset cancellation loop is implemented to remove the DC offset of the limiting amplifier. To minimize the lowfrequency pattern-dependent jitter associated with this DC-cancellation loop, the low-frequency cutoff is 10kHz (typ) with CAZ = 0.1F, connected from CAZ+ to CAZ-. The DC-offset cancellation loop operates only when threshold adjust is disabled.
Table 1. Operational Modes
MODE Normal System loopback Clock holdover LREF 1 1 0 SIS 0 1 1 or 0
Design Procedure
Decision Threshold Adjust
In applications in which the noise density is not balanced between logical zeros and ones (i.e., optical amplification using EDFA amplifiers), lower bit-error ratios (BERs) can be achieved by adjusting the input threshold. Varying the voltage at VCTRL from +0.3V to +2.1V achieves a vertical decision threshold adjustment of +170mV to -170mV, respectively (Figure 2). Use the provided bandgap reference voltage output (VREF) with a voltage-divider circuit or the output of a DAC to set the voltage at VCTRL. See Figure 10 when using VREF to generate the voltage for VCTRL. VREF can be used to generate the voltage for VCTRL (Figure 10). If threshold adjust is not required, disable it by connecting VCTRL directly to VCC and leave VREF floating.
Table 2. Data-Rate Settings (MAX3874)
INPUT DATA RATE (Gbps) 2.667 2.488 RATESET 1 0 FREFSET 1 or 0 1 or 0
Table 3. Data-Rate Settings (MAX3874A)
INPUT DATA RATE (Gbps) 2.0212 RATESET 0 FREFSET 1 or 0
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2.488Gbps/2.667Gbps Clock and Data Recovery with Limiting Amplifier MAX3874
Table 4. Holdover Frequency Settings
REFERENCE CLOCK FREQUENCY (MHz) 666.51 622.08 166.63 155.52 SCLKO FREQUENCY (GHz) 2.667 2.488 2.667 2.488 RATESET 1 0 1 0 FREFSET 0 0 1 1
Setting the Loop Filter
The MAX3874 is designed for both regenerator and receiver applications. Its fully integrated PLL is a classic 2nd-order feedback system, with a jitter transfer bandwidth (JBW) below 2MHz. The external capacitor (CFIL) connected from FIL to VCC_VCO sets the PLL damping. Note that the PLL jitter transfer bandwidth does not change as CFIL changes, but the jitter peaking, acquisition time, and loop stability are affected. Figures 6 and 7 show the open-loop and closed-loop transfer functions. The PLL zero frequency, fZ, is a function of external capacitor CFIL, and can be approximated according to: fZ = 1 2(650)CFIL
HO(j2f) (dB)
OPEN-LOOP GAIN
CFIL = 0.068F fZ = 3.6kHz
CFIL = 0.01F fZ = 24.5kHz
f (kHz) 1 10 100 1000
Figure 6. Open-Loop Transfer Function
For an overdamped system (fZ / JBW < 0.25), the jitter peaking (JP) of a 2nd-order system can be approximated by:
H(j2f) (dB) CLOSED-LOOP GAIN CFIL = 0.01F
f JP = 20 log1 + Z JBW where JBW is the jitter transfer bandwidth for a given data rate. The recommended value of CFIL = 0.068F is to guarantee a maximum jitter peaking of less than 0.1dB. Decreasing C FIL from the recommended value decreases acquisition time, with the trade-off of increased peaking. Excessive reduction of CFIL can cause PLL instability. CFIL must be a low-TC, high-quality capacitor of type X7R or better.
0 -3 CFIL = 0.068F
f (kHz) 1 10 100 1000
Figure 7. Closed-Loop Transfer Function
Input Terminations
The SDI and SLBI inputs of the MAX3874 are current-mode-logic (CML) compatible. The inputs all provide internal 50 termination to reduce the required number of external components. AC-coupling is recom-
mended. See Figure 8 for the input structure. For additional information about logic interfacing, refer to Maxim Application Note HFAN 1.0: Introduction to LVDS, PECL, and CML.
10
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2.488Gbps/2.667Gbps Clock and Data Recovery with Limiting Amplifier MAX3874
VCC
MAX3874
VCC 50 SDI+ SDO+ 50 50 50
SDI-
SDO-
MAX3874
Figure 8. CML Input Model
Output Terminations
The MAX3874 uses CML for its high-speed digital outputs (SDO and SCLKO). The configuration of the output circuit includes internal 50 back terminations to VCC. See Figure 9 for the output structure. CML outputs can be terminated by 50 to VCC, or by 100 differential impedance. For additional information on logic interfacing, refer to Maxim Application Note HFAN 1.0: Introduction to LVDS, PECL, and CML.
Figure 9. CML Output Model
Consecutive Identical Digits (CIDs)
The MAX3874 has a low phase and frequency drift in the absence of data transitions. As a result, long runs of consecutive zeros and ones can be tolerated while maintaining a BER better than 10-10. The CID tolerance is tested using a 213 - 1 PRBS with long runs of ones and zeros inserted in the pattern. A CID tolerance of 2000 bits is typical.
Applications Information
Clock Holdover Capability
Clock holdover is required in some applications in which a valid clock must be provided to the upstream device in the absence of data transitions. To provide this function, an external reference clock signal must be applied to the SLBI inputs and the proper control signals set (see the Modes of Operation section). To enter holdover mode automatically when there are no transitions applied to the SDI+ inputs, LOL or the system LOS can be directly connected to LREF.
Exposed Pad (EP) Package
The EP, 32-pin QFN incorporates features that provide a very low thermal-resistance path for heat removal from the IC. The pad is electrical ground on the MAX3874 and should be soldered to the circuit board for proper thermal and electrical performance.
Layout Considerations
For best performance, use good high-frequency layout techniques. Filter voltage supplies, keep ground connections short, and use multiple vias where possible. Use controlled-impedance transmission lines to interface with the MAX3874 high-speed inputs and outputs. Place power-supply decoupling as close to VCC as possible. To reduce feedthrough, isolate the input signals from the output signals. If a bare die is used, mount the back of die to ground (GND) potential. Figure 10 shows interfacing with the MAX3861 AGC using threshold adjust.
11
System Loopback
The MAX3874 is designed to allow system-loopback testing. When the device is set for system-loopback mode, the serial output data of a transmitter can be directly connected to the SLBI inputs to run system diagnostics. See Table 1 for selecting system loopback operation mode. While in system loopback mode, LREF should not be connected to LOL.
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2.488Gbps/2.667Gbps Clock and Data Recovery with Limiting Amplifier MAX3874
+3.3V 0.1F +3.3V 0.068F FIL VCC_VCO CAZSDI+ TIA OUTPUT (2.488Gbps) MAX3861 AGC AMPLIFIER SDISLBI+ SLBIR1 155.52MHz REFERENCE CLOCK VCTRL VREF SIS R2 LREF LOL RATESET GND SDO+ CML CAZ+ +3.3V +3.3V VCC FREFSET
MAX3874
SDOSCLKO+ CML SCLKO-
R1 + R2 50k
TTL
Figure 10. Interfacing with the MAX3861 AGC Using Threshold Adjust
Pin Configuration
VCTRL CAZ+ CAZGND VCC GND VREF
Chip Information
TRANSISTOR COUNT: 5142 PROCESS: SiGe BiPolar SUBSTRATE: SOI
TOP VIEW
32
31
30
29
28
27
26
FREFSET
25
VCC SDI+ SDIVCC SLBI+ SLBISIS LREF
1 2 3 4 5 6 7 8 10 11 12 13 14 15 16 9
24 23 22 21
VCC_OUT SDO+ SDOVCC_OUT SCLKO+ SCLKOVCC_VCO RATESET
MAX3874
20 19 18 17
FIL
VCC_VCO
N.C.
N.C.
LOL
GND
12
______________________________________________________________________________________
GND
5mm x 5mm QFN
GND
2.488Gbps/2.667Gbps Clock and Data Recovery with Limiting Amplifier
Package Information
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to www.maxim-ic.com/packages.)
32L QFN.EPS
MAX3874
PACKAGE OUTLINE, 16,20,28,32L QFN, 5x5x0.90 MM 1
21-0091
I
2
PACKAGE OUTLINE, 16,20,28,32L QFN, 5x5x0.90 MM 2
21-0091
I
2
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 13 (c) 2003 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.

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